1. Field of the Invention
The present invention relates to a shift register circuit for use as, for example, a scanning line driving circuit in an image display apparatus and constituted by only field-effect transistors of the same conductivity type, and in particular to a bidirectional shift register that can reverse the direction of shift of a signal.
2. Description of the Background Art
In an image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display, a plurality of pixels are arranged in a matrix in a display panel and a gate line (scanning line) is provided for each row of pixels (pixel line) of the display panel. In a cycle of one horizontal period of a display signal, the gate lines are sequentially selected and driven to update a display image. As a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register may be used which performs a round of shift operation in one frame period of a display signal.
In order to reduce the number of steps in the manufacturing process of a display apparatus, a shift register for use as a gate line driving circuit should preferably be constituted by only field-effect transistors of the same conductivity type. Therefore, various shift registers constituted by only N- or P-type field-effect transistors and various display apparatuses containing such shift registers have been proposed. As a field-effect transistor, a MOS (Metal Oxide Semiconductor) transistor, a thin film transistor (TFT) or the like is used.
A gate line driving circuit is constituted by a shift register having a plurality of stages. Specifically, a gate line driving circuit is constituted by a plurality of cascade-connected shift register circuits, each of which is provided for each pixel line, i.e., each gate line. In this specification, for convenience of description, each of a plurality of shift register circuits which are constituents of a gate line driving circuit is referred to as a “unit shift register.”
For example in a matrix type liquid crystal display apparatus with a matrix of liquid crystal pixels, it is often requested to change the display pattern, such as to turn the display image upside down and from side to side and to change the order of display at the time of display.
Turning the display, for example, is desired when a translucent screen is used with a liquid crystal display applied to an OHP (overhead projector). This is because, in the case of using a translucent screen, an image is projected from the back side of the screen as viewed from a viewer, so that when projected from the front side of the screen, an image is inverted on the screen. Changing the order of display is desired when rendering effects, such as gradual appearance of a display image from top to bottom or from bottom to top, are required for display of a bar graph, a histogram, etc.
One of the techniques for changing the display pattern in a display apparatus is to switch the direction of shift of a signal in a gate line driving circuit. For this, shift registers that can switch the direction of shift of a signal (hereinafter referred to as “bidirectional shift registers”) have been proposed.
For example, Japanese Patent Application Laid-open No. 2001-350438 (pp. 13-19, FIGS. 13-25) discloses in its FIG. 13, a unit shift register (hereinafter also referred to as a “bidirectional unit shift register) for use in a bidirectional shift register and constituted by only N-channel type field effect transistors (a similar circuit is shown in FIG. 3 of the specification of the present invention, and the reference numerals or characters in parentheses below correspond to those in FIG. 3 of the present invention).
An output stage of the unit shift register is constituted by a first transistor (Q1) that supplies a clock signal (CLK) inputted to a clock terminal (CK) to an output terminal (OUT), and a second transistor (Q2) that supplies a reference voltage (VSS) to the output terminal. Here, a gate node (N1) of the first transistor is defined as a first node, and a gate node (N2) of the second transistor as a second node.
The unit shift register includes a third transistor (Q3) that supplies a first voltage signal (Vn) to the first node based on a signal inputted to a predetermined first input terminal (IN1), and a fourth transistor (Q4) that supplies a second voltage signal (Vr) to the first node based on a signal inputted to a predetermined second input terminal (IN2). The first and second voltage signals are complementary to each other in such a way that when one of them is at a HIGH voltage level (voltage level is hereinafter referred to simply as a “level”), the other is at a LOW level.
The first transistor is driven by those third and fourth transistors. The second transistor is driven by an inverter (Q6, Q7) that uses the first node as the input end (input node) and the second node as the output end (output node). Specifically, when the unit shift register outputs an output signal, the second and third transistors operate to set the first node to HIGH level, and accordingly the inverter sets the second node to LOW level. Thereby, the first transistor is turned on and the second transistor is turned off, in which state a clock signal is transmitted to the output terminal which then outputs an output signal. On the other hand, when the unit shift register does not output an output signal, the second and third transistors operate to set the first node to LOW level, and accordingly the inverter sets the second node to HIGH level Thereby, the first transistor is turned off and the second transistor is turned on, in which state the voltage level of the output terminal is maintained LOW.
For example when the first voltage signal is at the HIGH level and the second voltage signal is at the LOW level, a signal input to the first input terminal causes the first node to become HIGH and accordingly the second node to become LOW, whereby the first transistor is turned on and the second transistor is turned off. Thus, the unit shift register outputs an output signal at a subsequent time when a clock signal is inputted. In other words, when the first voltage signal is HIGH and the second voltage signal is LOW, the unit shift register operates to time-shift and output a signal inputted to the first input terminal.
On the contrary, when the first voltage signal is at the LOW level and the second voltage signal is at the HIGH level, a signal input to the second input terminal causes the first node to become HIGH and accordingly the second node to become LOW, whereby the first transistor is turned on and the second transistor is turned off. Thus, the unit shift register outputs an output signal at a subsequent time when a clock signal is inputted. In other words, when the first voltage signal is LOW and the second voltage signal is HIGH, the unit shift register operates to time-shift and output a signal inputted to the second input terminal.
In this way, the bidirectional unit shift register disclosed in FIG. 13 of Japanese Patent Application Laid-open No. 2001-350438 (FIG. 3 of the specification of the present invention) switches the direction of shift of a signal by switching the levels of the first and second voltage signals for driving the first transistor.
As described above, a conventional bidirectional unit shift register circuit includes the output stage constituted by the first transistor (Q1) that supplies the clock signal (CLK) inputted to the clock terminal (CK) to the output terminal (OUT), and the second transistor (Q2) that supplies the reference voltage (VSS) to the output terminal. During the period when the unit shift register does not output an output signal (this period is hereinafter referred to as a “non-selected period”), the first transistor remains ON and the second transistor remains OFF, whereby the voltage level (hereinafter referred to simply as a “level”) of the output terminal is maintained LOW.
A display apparatus in which shift registers in a gate line driving circuit are constituted by amorphous silicon TFTs (a-Si TFTs), is easy to increase its area and has high productivity, so that it is widely adopted, for example, as a display screen of a notebook PC, a large-screen display or the like.
But, a-Si TFTs have a tendency that, when their gate electrodes are positively and continuously (dc) biased, their threshold voltages may shift in a positive direction, which causes impaired drive capabilities (capabilities to pass current). Especially in a shift register of a gate line driving circuit, during the non-selected period which is of the same length as about one frame period (approximately 16 ms), the gate of the second transistor is positively and continuously biased in order to turn the second transistor on. Repeating that operation impairs the drive capability of the second transistor. If that is the case, when unnecessary charges are supplied to the output terminal due to noise or the like, the second transistor cannot discharge those charges and such a malfunction results that the gate lines may be activated by mistake. It is known that a similar problem can occur not only in a-Si TFTs but also in, for example, organic TFTs.
On the other hand, Japanese Patent Application Laid-open No. 2006-24350 discloses in its FIG. 7, a unit shift register that can reduce the problem of this threshold voltage shift (Vth shift) (the reference numerals or characters in parentheses below correspond to those in FIG. 7 of Japanese Patent Application Laid-open No. 2006-24350).
The unit shift register shown in FIG. 7 of Japanese Patent Application Laid-open No. 2006-24350 includes two transistors (TdA, Td) corresponding to the second transistor, and a transistor (T1A) that prevents a rise in the level of the gate of a first transistor (Tu) during the non-selected period. When not selected, the unit shift register swings the levels of the gates of those three transistors (TdA, Td, T1A) in response to level transitions of clock signals (CLK, CKB). According to this technique, the threshold voltages of those three transistors (TdA, Td, T1A) will be ultimately settled to values that are almost intermediate between HIGH and LOW levels of the clock signals (CLK, CKB) (assuming that parasitic capacitances accompanying gate nodes of the transistors TdA, Td and T1A are extremely small and that the duty ratios of the clock signals (CLK, CKB) are 50%).
Although the unit shift register in FIG. 7 of Japanese Patent Application Laid-open No. 2006-24350 has only one fixed direction of shift of a signal (i.e., a unidirectional shift register), it can serve as a bidirectional unit shift register if the aforementioned first voltage signal (Vn) is supplied to the drain of the transistor T0 and the second voltage signal (Vr) is supplied to the source of the transistor T1 in the unit shift register.
Doing so, however, causes the following problem. Specifically, although the transistors T0 and T1 are off during the non-selected period, if they are activated by light or thermal energy from the outside of the display apparatus, off-state current will flow. Since either of the first voltage signal (Vn) and the second voltage signal (Vr) is always at the HIGH level, a high-level charge is supplied to the gate of the first transistor (Tu) through the transistor T0 or T1. Consequently, there is concern that the level of the gate of the first transistor (Tu) might rise during the non-selected period. The problem is that if, at this time, the level of the gate exceeds the threshold voltage of the first transistor (Tu), an error output signal will be outputted.
As described above, the unit shift register shown in FIG. 7 of Japanese Patent Application Laid-open No. 2006-24350 includes the transistor T1A in order to prevent the occurrence of such a problem. However, since the gate of the transistor T1A swings in response to a clock signal, the transistor T1A is turned off associated with the cycle of the clock signal. Accordingly, if a large off-state current flows through the transistors T0 and T1, the level of the gate of the first transistor Tu might exceed the threshold voltage thereof during the off period of the transistor T1A.